Design and Implementation of High Performance Reed Solomon Encoder and Decoder

In this paper, Reed Solomon (RS) Encoder and Decoder and their implementation in Spartan 6 Field Programmable Gate Array (FPGA) is analyzed. RS codes are non-binary cyclic error correcting block codes. Here parity symbols are generated at the encoder end using a generator polynomial and added to the very end of the message symbols. Then the locations and magnitudes of errors in the received polynomial are determined by the RS decoder. The main objective of this project is to optimize the area used on FPGA which in turn minimizes the size and ultimately the cost. The paper covers the RS encoding and decoding algorithm, simulations and the implementation details of the encoder and decoder architecture. Register transfer level (RTL) of RS encoder and decoder is designed, simulated and implemented using Xilinx in Spartan 6 FPGA kit.

Keywords: FPGA, Key Equation Solver (KES), Reed Solomon (RS) Decoder, Reed Solomon (RS) Encoder and VHDL.