VHDL implementation of a Novel Low Power Squaring Circuit Using YTVY Algorithm of Vedic Mathematics

Squaring plays an important role in VLSI signal processing applications. The multiplier piece is used to square of a number in much complex multiplication. For carrying out the large hardware circuit, the multiplier unit is most efficient and time consuming. In multiplier unit, the squaring operation is unique case. A exclusive and proper squaring circuit can be a remarkable upgrade the computation time and in the power reduction to a large extend. Ingeneral, the squaring circuits use very fast multiplier. A innovative idea of a squaring circuit without using multiplier is suggested in this paper. In this paper, we have implemented a novel algorithm Yavadunam Tavadunikrtya Vargarica Yojayet (YTVY) of ancient vedic mathematics for the squaring operation circuit. The main advantage of this paper is that no multiplier is used for the squaring circuit. The circuit is designed with the help of VHDLlanguages and synthesized in Xilinx ISE Design Suite 14.1.

Keywords: Squaring Circuit, VLSI Signal Processing,YTVY Sutra, Vedic Mathematics,FPGA,VHDL