Efficient iSLIP Arbiter with iSLIP Scheduling Algorithm for NoC

Increasing complexity of the individual devices, the increasing demand for higher bandwidth on the network lines and an operating frequency hitting new limits with almost every new design, place the communication and computation resources arbitration being the performance bottleneck of the NoC system.  The arbitration is desired to be completed within one clock cycle to avoid large latencies between the cores on the chip. To achieve the arbitration in one clock cycle, the total delay introduced by the arbitration should be low so that it will not impact the overall system clock frequency which introduces new challenges for the design of the arbiters. In this paper, we design iSLIP arbiter using iSLIP scheduling algorithm with mesh router for NoC. An iterative, round-robin algorithm, iSLIP can achieve 100% throughput for uniform traffic. It is well known that if simple first in first out (FIFO) input queues are used to hold packets then, even under benign conditions, head-of-line (HOL) blocking limits the achievable bandwidth to approximately 58.6% of the maximum. HOL blocking can be overcome by the use of virtual output queuing, which is described in this paper. It is designed using VHDL and using ModelSimSE 6.3f.

Keywords: iSLIP,  iterative, scheduling algorithm, mesh router, arbiter