Design and Implementation of 4-bit Pipeline ADC using 0.09µm CMOS Technology

This paper focuses on design and implementation of 1.1V, 4-bit Pipeline Analog to Digital Converter [ADC]. The ADC consists of sample and hold, latched comparator and summing circuit and amplifier of gain 2. The ADC has been designed and simulated in standard gpdk90ηm CMOS technology library using Cadence tool.

Keywords: ADC, CMOS, gpdk90ηm.